A local resistance term reduced steady soma voltage error below 0.034% RMS in ten passive path models with 10 µm bins and 1 nS inputs

A compact neuron model must keep the effect of each synapse's position. We tested a local resistance term for inputs between retained voltage nodes. The test used ten measured dendrite diameter profiles as isolated passive paths. Each coarse bin kept its membrane area and axial resistance. In the main test, each path received 32 separate steady 1 nS inputs. With 10 µm bins, the largest root mean square (RMS) relative soma voltage error was 0.0332%. Attachment to the nearest node gave path errors of 0.865–3.694%. The local term added no voltage state. Across 60 brief-input cases, the largest corrected soma waveform error was 0.158%. Two simultaneous inputs also required their shared local resistance. A tenfold faster pulse with 50 µm bins raised the largest local waveform error to 12.93%. The circuit calculation follows established node elimination. The contribution is an implementation and a reproducible benchmark on these profiles. The errors compare passive models of the same geometry. Branching, active channels, and recorded synaptic responses remain untested. The package contains source data, provenance, code, result tables, and figures.

dendrite · synaptic conductance · model reduction · input resistance · synapse location · passive cable · reproducible benchmark